VSC6511 Datasheet, PDF (11/22 Pages) Vitesse Semiconductor Corporation – SMPTE-292M Serializer, Deserializer, and Deserializer/Reclocker at 1.485Gb/s

VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC6511
SMPTE-292M Serializer, Deserializer, and
Deserializer/Reclocker at 1.485Gb/s
Functional Description: Deserializer Mode
The following functional blocks are used in the Deserializer mode of operation. Please refer to the Func-
tional Description at the beginning of this document for the a description of each of these blocks.
Clock Multiplier Unit (CMU)
Serial Input
Clock Recovery Unit
Deserializer
Descrambler and NRZI Decoder
CRC Checker
Frame Aligner and SAV/EAV output
Figure 6: Receive Timing Waveforms (Deserializer Mode)
RCLK
D[0:19]
LINE
FRAME
CRCERR
T₁
T₂
Data Valid
Table 5: Receive AC Characteristics (Deserializer Mode)
Parameters
T₁
T₂
T_R, T_F
T_LOCK
Description
TTL Outputs alid prior to
RCLK rise
TTL Outputs valid after
RCLK rise
TTL Output rise and fall
time
Data acquisition lock time
@ 1.485 Gb/s
Min.
3.0
2.0
—
—
Max.
—
—
2.0
TBC
Note: The RCLK output from the CRU is 40% high and 60% low by design.
Units
ns.
Conditions
ns.
ns.
Between V_IL(MAX) and
V_IH(MIN), into 10 pf. load.
ms.
G52311-0, Rev. 2.0
4/10/00
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