VSC6511 Datasheet, PDF (10/22 Pages) Vitesse Semiconductor Corporation – SMPTE-292M Serializer, Deserializer, and Deserializer/Reclocker at 1.485Gb/s

VITESSE
SEMICONDUCTOR CORPORATION
SMPTE-292M Serializer, Deserializer, and
Deserializer/Reclocker at 1.485Gb/s
Advance Product Information
VSC6511
Features: Deserializer Mode
1. Compliant with SMPTE-292M @ 1.485Gb/s
2. Clock and Data Recovery
3. 1:20 Deserializer
4. Descrambler and NRZI Decoder with ENABLE
5. Data Framer aligns data to SAV/EAV
6. On-chip Clock Multiplier Unit
7. CRC Checker
8. LINE, FRAME, HANC Indication
9. 3.3V, 800 mW -- typical power
10. 20 Bit TTL Interface @ 74.25 MHz
General Description
The VSC6511 can be configured as a 20-bit HDTV Deserializer using the MODE[1:0] pins. Serial data
from SDI/SDI is sent to the Clock Recovery Unit (CRU) for clock extraction and data resynchronization. Then
the serial data is descrambled/NRZI decoded, deserialized and output on D[19:0] synchronously by a divided-
by-twenty recovered clock, RCLK. A CRC Checker monitors the output data and indicates any CRC errors on
the CRC pin. Descrambling is enabled by SCREN being HIGH. Data framing aligns the SAV/EAV patterns in
the data with the data bus and RCLK and generates a once-per-line and once-per-frame synchronization output.
A signal detect function on SDI/SDI monitors the quality of the serial input.
Figure 5: Deserializer Mode
D[19:0]
SCREN
SDI
SDI
REFCLK
74.25 MHz
Clock
Recovery
Unit
Deserializer
1.485 GHz
/20
Clock
Multiply
x20
1.485 GHz
NRZI Decoder
Descrambler
CRC Check ^{D Q}
Framer
SIGDET
CRCERR
LINE
FRAME
HANC
1001
RCLK
Page 10
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]
G52311-0, Rev 2.0
4/10/00