VSC6511 Datasheet, PDF (13/22 Pages) Vitesse Semiconductor Corporation – SMPTE-292M Serializer, Deserializer, and Deserializer/Reclocker at 1.485Gb/s

VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC6511
SMPTE-292M Serializer, Deserializer, and
Deserializer/Reclocker at 1.485Gb/s
REFCLK
Figure 8: REFCLK Timing Waveforms: All Modes
T_L
T_H
T_R
V_IH(MIN)
V_IL(MAX)
Table 6: Reference Clock Requirements *
Parameters
Description
Min Max Units
Conditions
FR
Frequency Range
FO
Frequency Offset
DC
REFCLK duty cycle
T_H, T_L
REFCLK high/low times
T_R
REFCLK rise
Note: The PLL locks to the rising edge of REFCLK.
73.75 74.50
-1000 1000
-15 +15
3.0
—
—
2.0
MHz
ppm.
%
ns.
ns.
Will accept both 74.176/74.25MHz
Difference in REFCLK frequencies
between the transmitting and
receiving VSC6511s.
Measured at 1.5V
Measured between V_IL(MAX) to
V_IL(MAX) or V_IH(MIN) to V_IH(MIN)
Between V_IL(MAX) and V_IH(MIN)
Figure 9: RCLK Timing Waveforms*
RCLK
T_L
T_H
T_R
V_IH(MIN)
V_IL(MAX)
Table 7: RCLK Performance - Deserializer and Deserializer/Reclocker Mode
Parameters
F_OFFSET
Description
RCLK Frequency offset from
REFCLK
Min Max Units
-1.0 +1.0
%
DC
RCLK duty cycle - 40% / 60% -5
+5
%
T_H
RCLK high times
3
—
ns.
T_L
RCLK low times
5.9
—
ns.
T_R
RCLK rise/fall time
—
1.5
ns.
Note: The RCLK output from the CRU is 40% high and 60% low by design.
Conditions
Maximum deviation when the CRU is
not locked. Deserializer Mode.
Measured at 1.5V. Deserializer Mode
and Deserializer/Reclocker Mode.
Measured between V_IH(MIN) to
V_IH(MIN)
Measured between V_IL(MAX) to
V_IL(MAX)
Between V_IL(MAX) and V_IH(MIN)
G52311-0, Rev. 2.0
4/10/00
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741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]
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