SI8429DB-T1-E1 Datasheet, PDF (7/11 Pages) Vishay Siliconix – P-Channel 1.2 V (G-S) MOSFET

PACKAGE OUTLINE
MICRO FOOT: 4-BUMP (0.8 mm PITCH)
Si8429DB
Vishay Siliconix
e
e
Recommended Land
4 x φ0.30 0.31
Note 3
Solder Mask φ 0.40
A₂
A
A₁
b Diamerter
Silicon
Bump Note 2
S
E
e
8429
XXX
Mark on Backside of Die
e
S
D
Notes (unless otherwise specified):
1. Laser mark on the silicon die back, coated with a thin metal.
2. Bumps are Sn/Ag/Cu.
3. Non-solder mask defined copper landing pad.
4. The flat side of wafers is oriented at the bottom.
Dim.
A
A₁
A₂
b
D
E
e
S
Min.
0.600
0.260
0.340
0.370
1.520
1.520
0.360
Notes:
a. Use millimeters as the primary measurement
Millimeters^a
0.800
Max.
0.650
0.290
0.360
0.410
1.600
1.600
0.400
Min.
0.0236
0.0102
0.0134
0.0146
0.0598
0.0598
0.0142
Inches
0.0315
Max.
0.0256
0.0114
0.0142
0.0161
0.0630
0.0630
0.0157
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?74399.
Document Number: 74399
For technical questions, contact: [e-mail]
www.vishay.com
S13-1847-Rev.D, 19-Aug-13
7
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000