SI4500BDY Datasheet, PDF (2/8 Pages) Vishay Siliconix – Complementary MOSFET Half-Bridge (N- and P-Channel)

Si4500BDY
Vishay Siliconix
SPECIFICATIONS (T_J = 25_C UNLESS OTHERWISE NOTED)
Parameter
Symbol
Test Condition
Static
Gate Threshold Voltage
V_GS(th)
V_DS = V_GS, I_D = 250 mA
V_DS = V_GS, I_D = −250 mA
Gate-Body Leakage
I_GSS
V_DS = 0 V, V_GS = "12 V
Zero Gate Voltage Drain Current
On-State Drain Current^b
Drain-Source On-State Resistance^b
Forward Transconductance^b
Diode Forward Voltage^b
Dynamic^a
I_DSS
I_D(on)
r_DS(on)
g_fs
V_SD
V_DS = 20 V, V_GS = 0 V
V_DS = −16 V, V_GS = 0 V
V_DS = 20 V, V_GS = 0 V, T_J = 55_C
V_DS = −16 V, V_GS = 0 V, T_J = 55_C
V_DS = 5 V, V_GS = 4.5 V
V_DS = −5 V, V_GS = −4.5 V
V_GS = 4.5 V, I_D = 9.1 A
V_GS = −4.5 V, I_D = −5.3 A
V_GS = 2.5 V, I_D = 3.3 A
V_GS = −2.5 V, I_D = −1 A
V_DS = 15 V, I_D = 9.1 A
V_DS = −15 V, I_D = −5.3 A
I_S = 2.1 A, V_GS = 0 V
I_S = −2.1 A, V_GS = 0 V
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Q_g
N-Channel
V_DS = 10 V, V_GS = 4.5 V, I_D = 9.1 A
Q_gs
P-Channel
V_DS = −10 V, V_GS = −4.5 V, I_D = −5.3 A
Q_gd
Turn-On Delay Time
t_d(on)
Rise Time
t_r
Turn-Off Delay Time
t_d(off)
Fall Time
t_f
Source-Drain Reverse Recovery Time
t_rr
Notes
a. Guaranteed by design, not subject to production testing.
b. Pulse test; pulse width v 300 ms, duty cycle v 2%.
N-Channel
V_DD = 10 V, R_L = 10 W
I_D ^ 1 A, V_GEN = 10 V, R_g = 6 W
P-Channel
V_DD = −10 V, R_L = 10 W
I_D ^ −1 A, V_GEN = −4.5 V, R_g = 6 W
I_F = 2.1 A, di/dt = 100 A/ms
I_F = −2.1 A, di/dt = 100 A/ms
Min Typ^a Max Unit
N-Ch
P-Ch
0.6
−0.6
1.5
V
−1.5
N-Ch
P-Ch
"100
nA
"100
N-Ch
1
P-Ch
N-Ch
−1
mA
5
P-Ch
−5
N-Ch
30
A
P-Ch
−20
N-Ch
P-Ch
N-Ch
0.016 0.020
0.048 0.060
W
0.024 0.030
P-Ch
0.082 0.100
N-Ch
29
S
P-Ch
11
N-Ch
P-Ch
0.8
1.2
V
−0.8
−1.2
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
11
17
6.0
9
2.5
nC
1.3
3.2
1.6
35
50
20
30
50
80
35
60
31
50
ns
55
85
15
30
35
60
30
60
25
50
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2
Document Number: 72281
S-41428—Rev. B, 26-Jul-04