TC55VEM208ASTN55 Datasheet, PDF (9/11 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

TC55VEM208ASTN40,55
DATA RETENTION CHARACTERISTICS (Ta = −40° to 85°C)
SYMBOL
PARAMETER
MIN
V_DH
I_DDS2
t_CDR
t_R
Data Retention Supply Voltage
1.5
Standby Current
V_DH = 3.6 V Ta = −40~85°C

Ta = −40~40°C

V_DH = 3.0 V
Ta = −40~85°C

Chip Deselect to Data Retention Mode Time
0
Recovery Time
5
TYP






MAX
3.6
10
2
5


UNIT
V
µA
ns
ms
CE CONTROLLED DATA RETENTION MODE
V_DD
V_DD
DATA RETENTION MODE
2.3 V
V_IH
CE
GND
(See Note)
t_CDR
V_DD − 0.2 V
(See Note)
t_R
Note: When CE is operating at the VIH(min.) level, the operating current is given by IDDS1 during the transition
of VDD from 2.3(2.7) to 2.2V(2.4 V).
2002-08-07 9/11