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TC55VEM208ASTN55 Datasheet, PDF (3/11 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
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TC55VEM208ASTN40,55
DC RECOMMENDED OPERATING CONDITIONS (Ta = −40° to 85°C)
SYMBOL
PARAMETER
VDD
Power Supply Voltage
VIH
Input High Voltage
VDD = 2.3 V~2.7 V
VDD = 2.7 V~3.6 V
VIL
Input Low Voltage
VDH
Data Retention Supply Voltage
*: −2.0 V when measured at a pulse width of 20ns
MIN
2.3
2.0
2.2
−0.3*
1.5
TYP
MAX
UNIT

3.6
V

VDD + 0.3
V

VDD × 0.24
V

3.6
V
DC CHARACTERISTICS (Ta = −40° to 85°C, VDD = 2.3 to 3.6 V)
SYMBOL PARAMETER
TEST CONDITION
MIN TYP MAX UNIT
IIL
Input Leakage
Current
VIN = 0 V~VDD
IOH
Output High Current VOH = VDD − 0.5 V
IOL
Output Low Current VOL = 0.4 V
ILO
Output Leakage
Current
CE = VIH or R/W = VIL or OE = VIH, VOUT = 0 V~VDD
  ±1.0 µA
−0.5 
2.1 
 mA
 mA
  ±1.0 µA
IDDO1
IDDO2
Operating Current
CE = VIL and R/W = VIH,
IOUT = 0 mA,
Other Input = VIH/VIL
CE = 0.2 V and R/W = VDD − 0.2 V,
IOUT = 0 mA,
Other Input = VDD − 0.2 V/0.2 V
MIN
tcycle
1 µs
MIN
1 µs
  35
mA
 8
  30
mA
 3
IDDS1
CE = VIH
IDDS2
Standby Current
CE = VDD − 0.2 V
  1 mA
VDD =
3.3V± 0.3 V
Ta = −40~85°C


10
Ta = 25°C
 0.7  µA
VDD =3.0 V Ta = −40~40°C   2
Ta = −40~85°C   5
CAPACITANCE (Ta = 25°C, f = 1 MHz)
SYMBOL
PARAMETER
TEST CONDITION
CIN
COUT
Input Capacitance
Output Capacitance
VIN = GND
VOUT = GND
Note: This parameter is periodically sampled and is not 100% tested.
MAX
10
10
UNIT
pF
pF
2002-08-07 3/11
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