TC55VEM208ASTN55 Datasheet, PDF(6/11 Page) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

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TC55VEM208ASTN55 Datasheet, PDF (6/11 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

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AC TEST CONDITIONS

PARAMETER

Input pulse level

tR, tF

Timing measurements

Reference level

Output load

Fig.1 : Input rise and fall time

VDD Typ

GND

10%

90%

1 V/ns

90%

10%

1 V/ns

TC55VEM208ASTN40,55

TEST CONDITION

0.2 V, VDD Ã 0.7 V + 0.2 V

1V / ns(Fig.1)

VDD Ã 0.5

30 pF + 1 TTL Gate(Fig.2)

Fig.2 : Output load

VTM

Dout

30 pF

R1 = 810 â¦

R2 = 1610 â¦

VTM = 2.3 V

2002-08-07 6/11

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