TC55VEM208ASTN55 Datasheet, PDF (2/11 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

BLOCK DIAGRAM
A7
A8
A9
A11
A12
A13
A14
A15
A16
A17
A18
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
TC55VEM208ASTN40,55
CE
MEMORY CELL ARRAY
2,048 × 256 × 8
(4,194,304)
V_DD
GND
8
SENSE AMP
COLUMN ADDRESS
DECODER
COLUMN ADDERSS
REGISTER
COLUMN ADDRESS
BUFFER
CE
A0 A1 A2 A3 A4 A5 A6 A10
OE
R/W
CE
CE
OPERATING MODE
MODE
Read
Write
Output Deselect
Standby
* = don't care
H = logic high
L = logic low
CE
OE
L
L
L
*
L
H
H
*
MAXIMUM RATINGS
SYMBOL
RATING
V_DD
Power Supply Voltage
V_IN
Input Voltage
V_I/O
Input/Output Voltage
P_D
Power Dissipation
T_solder
Soldering Temperature (10s)
T_stg
Storage Temperature
T_opr
Operating Temperature
*: −2.0 V when measured at a pulse width of 20ns
R/W
I/O1~I/O8
H
Output
L
Input
H
High-Z
*
High-Z
POWER
I_DDO
I_DDO
I_DDO
I_DDS
VALUE
−0.3~4.2
−0.3*~4.2
−0.5~V_DD + 0.5
0.6
260
−55~150
−40~85
UNIT
V
V
V
W
°C
°C
°C
2002-08-07 2/11