TC55VEM208ASTN55 Datasheet, PDF (4/11 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

TC55VEM208ASTN40,55
AC CHARACTERISTICS AND OPERATING CONDITIONS
(Ta = −40° to 85°C, V_DD = 2.7 to 3.6 V)
READ CYCLE
SYMBOL
PARAMETER
t_RC
t_ACC
t_CO
t_OE
t_COE
t_OEE
t_OD
t_ODO
t_OH
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable Low to Output Active
Output Enable Low to Output Active
Chip Enable High to Output High-Z
Output Enable High to Output High-Z
Output Data Hold Time
TC55VEM208ASTN
40
55
MIN MAX MIN MAX
40

55


40

55

40

55

25

30
5

5

0

0


20

25

20

25
10

10

UNIT
ns
WRITE CYCLE
TC55VEM208ASTN
SYMBOL
PARAMETER
40
55
UNIT
MIN MAX MIN MAX
t_WC
Write Cycle Time
40

55

t_WP
Write Pulse Width
30

40

t_CW
Chip Enable to End of Write
35

45

t_AS
Address Setup Time
0

0

t_WR
Write Recovery Time
0

0

ns
t_ODW
R/W Low to Output High-Z

20

25
t_OEW
R/W High to Output Active
0

0

t_DS
Data Setup Time
20

25

t_DH
Data Hold Time
0

0

Note: t_OD, t_ODO and t_ODW are specified in time when an output becomes high impedance, and are not judged depending on an
output voltage level.
2002-08-07 4/11