TC55VEM208ASTN55 Datasheet, PDF (8/11 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

WRITE CYCLE 2 (CE CONTROLLED) ^{(See Note 4)}
TC55VEM208ASTN40,55
Address
A0~A18
R/W
CE
D_OUT
I/O1~8
D_IN
I/O1~8
t_AS
t_COE
Hi-Z
(See Note 5)
t_WC
t_WP
t_WR
t_CW
t_ODW
Hi-Z
t_DS
t_DH
VALID DATA IN
(See Note 5)
Note:
(1)
(2)
(3)
(4)
(5)
R/W remains HIGH for the read cycle.
If CE goes LOW coincident with or after R/W goes LOW, the outputs will remain at high impedance.
If CE goes HIGH coincident with or before R/W goes HIGH, the outputs will remain at high impedance.
If OE is HIGH during the write cycle, the outputs will remain at high impedance.
Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be
applied.
2002-08-07 8/11