TX19A Datasheet, PDF (89/491 Pages) Toshiba Semiconductor – 32Bit TX System RISC

Chapter 5 CPU Pipeline
5.2.3 Store Instructions (32 Bit ISA/ 16 Bit ISA)
Figure 5-6 illustrates how the store instruction advances through the CPU pipeline.
F
Instruction
Fetch
D
E
M
W
Decode
Effective Address
Calculation &
Bus Cycle Initiation
Mempory Access
in WAIT
―
Figure 5-6 Store Instruction
Stores to the on-chip fast memory occur during the Memory Access (M) stage; no operation occurs
in the Register Write-back (W) stage. Stores to external memory take more than one cycle.
The store instruction is to store the data in CPU register to the memory. Figure 5-7 shows how to store
to the on-chip fast memory. Stores to the on-chip fast memory occur during the Effective Address
Calculation (E) stage and they take 1 clock as a write bus cycle. No operations occur in the Memory
Access stage and the Register Write-back stage.
Figure 5－8 shows the procedure to execute the instruction on the external memory access. Stores to
the external memory take more than 2 clocks as a write bus cycle. With the TX19A, the pipelines
never stall by the continuous memory access instructions because its on-chip write buffer can store 4
write-data at the maximum. The instructions using subsequent write buffer stall when the write buffer
space is full.
Write Cycle
Bus Cycle
SW
ADDU
ADDU
r3,4(r2)
r4,r3,r2
r5,r6,r7
F D E MW
F D E MW
F D E MW
Figure 5-7 Access to the On-chip Fast Memory
Bus Cycle
Write Cycle
Instruction1 Instruction2 Instruction3
Write Buffer
Instruction 1 SW r4,4(r2)
F D E MW
Instruction 2 SW r5,8(r2)
F D E MW
Instruction 3 SW r6,12(r2)
F D E MW
Figure 5-8 Continuous Access to the External Memory
5-5