TX19A Datasheet, PDF (3/491 Pages) Toshiba Semiconductor – 32Bit TX System RISC

Preface
This manual describes the architecture of the Toshiba TX19A family.
Contents
Chapter 1: Introduction
Outline of TX19A
Chapter 2: CPU Architecture Overview
-Data load in the CPU registers and memory
-Overview of the functionality of the registers
Chapter 3: 32-Bit ISA Summary and Programming Tips
-Summary of the 32-bit instruction set architecture (ISA)
Chapter 4: 16-Bit ISA Summary and Programming Tips
-Summary of the 16-bit ISA
Chapter 5: CPU Pipeline
-Information about the instruction pipeline
Chapter 6: Memory Management
-The virtual and physical address spaces and these mapping manners
Chapter 7: Internal I/O Bus Operation
-Outlines of the Harvard architecture and the protocols for internal bus transactions
Chapter 8: System Control Coprocessor (CP0) Registers
-A group of registers associated with system configuration and exception processing
Chapter 9: CPU Exception Processing
-The events that cause exceptions and the sequences to be handled
Chapter 10: Power Consumption Management
-The methods of dynamically controlling power consumption during operation
Appendix A: 32-Bit ISA Details
-Detailed description of each instruction available in 32-bit ISA mode
Appendix B: 16-Bit ISA Details
-Detailed description of each instruction available in 16-bit ISA mode
Appendix C: Programming Restrictions
-The restrictions need to be observed in writing assembly-language programs
Appendix D: Compatibility Among TX19, TX19A and TX39 Architectures
-Provides comparisons among the three RISC processor families
Appendix E: 32-Bit ISA Instruction Bit Encoding
-The opcode bit encoding for the 32-bit ISA
Appendix F: 16-Bit ISA Instruction Bit Encoding
-the opcode bit encoding for the 16-bit ISA
March.2007
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