TX19A Datasheet, PDF (347/491 Pages) Toshiba Semiconductor – 32Bit TX System RISC

Appendix B 16-Bit ISA Details
ERET
Exception Return
Operation
if Status[ERL] = 1 then pc ⇐ Error EPC
Status[ERL] ⇐ 0
else pc ⇐ EPC
Status[EXL] ⇐ 0
SSCR[CSS] ⇐ SSCR[PSS]
Instruction Encoding
31
27 26
22 21
EXTEND
11110
01000
5
5
000000
6
16 15
11 10
11101
5
000000
6
54
0
11000
EXTENDED
5
Description
ERET is an instruction for returning from an interrupt, exception or error trap.
The ERET instruction does not have a delay slot. It is executed with a delay of one instruction (two
pipeline cycles).
The ERET instruction restores the ISA mode bit (bit 0) of the PC from bit 0 of the ErrorEPC
register, bringing the processor into the ISA mode that had been in effect before the exception was
taken.
An attempt to execute the ERET instruction in User mode when the CU0 bit in the Status register is
cleared causes a Coprocessor Unusable exception. If you want to use the MTC0 instruction to load
the ErrorEPC or EPC register with a return address or if you have modified the contents of the
Status register, the exception handler must execute at least two instructions before issuing the ERET
instruction.
If the ERL bit in the Status register is set, ERET restores the PC from the ErrorPC register and then
clears the ERL bit. Otherwise, ERET restores the PC from the EPC register and then clears the EXL
bit.
Also, the PSS field in the SSCR register is popped to the CSS field.
ERET must not be placed in a branch or jump delay slot.
B-65