TX19A Datasheet, PDF (315/491 Pages) Toshiba Semiconductor – 32Bit TX System RISC

Appendix B 16-Bit ISA Details
BEXT offset (fp), pos3
Bit Extract
Operation
t8 ⇐ 31’b 000_0000_0000_0000_0000_0000_0000_0000 || {zero-extend (offset) + (fp)} [pos3]
Instruction Encoding
15
11 10 8 7 5 4
0
11111
bext
pos3 offset[4:0]
101
5
3
3
5
Description
A bit specified by pos3 in a memory byte is copied into the least-significant bit (LSB) of general
purpose register t8 (r24). The upper 31 bits of t8 are filled with zeros. The effective address is
computed by zero-extending the 5-bit offset and adding the resultant value to the contents of the fp
register (r30).
With the 5-bit offset5 field, the offset range is 0 to +31.
Exceptions
Address Error exception
Example
Assume that the fp register (r30) contains 0x0000_0400 and that the byte position at address 0x0404
contains 0xF2. Then, the instruction:
BEXT 4(fp), 3
loads r24 with 0x0000_0000.
r30 ^0x0000_0400
0x400
0x401
+4 ^0x402
0x403
0x404
Memory
Byte
11110010
r24 0x0000_0000
Bit 3 is loaded into r24.
B-33