TX19A Datasheet, PDF (376/491 Pages) Toshiba Semiconductor – 32Bit TX System RISC

Appendix B 16-Bit ISA Details
Example
LHU r3,4(r2)
Assume that register r2 contains 0x0000_0400 and that the memory locations at addresses 0x404
and 0x405 contain 0xFF and 0x02 respectively. Since the offset value is shifted left by one bit by
the processor hardware, the assembler/linker turns the specified offset (4 or binary 0100) into a code
of 2 (binary 0010). Thus the instruction code for this load instruction becomes 0xAA62.
This load instruction loads register r3 with 0x0000_FF02 in big-endian mode and with
0x0000_02FF in little-endian mode.
r2 ^0x0000_0400
+4
The offset, 2, is
shifted left by 1 bit.
r3 0x0000_FF02
Big-Endian
r3 0x0000_02FF
Little-Endian
0x400
0x401
0x402
0x403
0x404
0x405
Memory
Byte
11111111
00000010
Load (Zero-Extended)
Halfword Boundary
Halfword Boundary
Halfword Boundary
Memory
CPU
Register
Zero-Extended
Halfword
Ø
B-94