TC9WMB4FU Datasheet, PDF (6/17 Pages) Toshiba Semiconductor – CMOS Digital Integrated Circuits Silicon Monolithic 4096-Bit (512 × 8-Bit) 2-Wire Serial EEPROM

TC9WMB4FU
(3) Acknowledge polling
Acknowledge polling is a feature for determining whether rewrite operation is in progress. During
rewrite operation, generate a start condition followed by a device address, and R/W (= 0 or 1). The
acknowledge feature does not generate an acknowledge signal while rewrite operation is in progress.
A low acknowledge signal is generated if rewriting has already completed.
If the next instruction is a write, supply a word address and write data subsequently. If the next
instruction is a read, supply a stop condition and then start read operation.
(4) Write protection
When “high” is received to the write protection (WP) pin, the device caused to protect the bottom
half (100h to 1FFh) of the memory area from being written. Rewriting is allowed when “low” is
received to the write protection pin. While a write is in progress, driving the WP pin high does not
stop write operation.
Reading is always enabled regardless of whether the WP pin is high or low.
6. Read Operation
Read operation is performed in one of three modes: current address read, random read, and sequential
read.
For reading, a device receives a device address and R/W (= 1) after a start condition. After read data is
sent, terminate a read operation by generating a high acknowledge signal (or releasing the bus without
supplying an acknowledge signal) and then supplying a stop condition.
(1) Current address read
The internal address counter maintains the address that is next to the last accessed (read or
written) word address (n). In current address read mode, data is read from address n + 1, as indicated
by the address counter.
In current address read mode, supplying a device address and R/W (= 1) after a start condition,
causes the device to generate a low acknowledge signal and send a data at the address indicated by
the internal address counter. In this case, the page address bit (P0) is ignored and a data is read at
the current address indicated by the internal address counter.
The address counter is incremented on the falling edge of the SCL pulse where a data at the eighth
bit is sent. If the previous operation was reading data from the last address, the current address is
rolled over to address 0. If the previous operation was writing data to the last address of the page, the
address is rolled over to the first address of the page.
The current address is maintained in an internal register so that it is lost when the power is turned
off. For the first read after power-up, specify an address by performing a random read.
S
T
R
S
A
E
T
R ^DEVICE A
O
T ADDRESS D
P
SDA LINE
1
0
1
0
A
2
A
1
×
1
DDDDDDDD
76543210
M
LRA
READ
N
S
S/C
DATA
O
B
BWK
A
C
K
Address
increment
Figure 7
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2007-10-19