TC9WMB4FU Datasheet, PDF(4/17 Page) Toshiba Semiconductor – CMOS Digital Integrated Circuits Silicon Monolithic 4096-Bit (512 × 8-Bit) 2-Wire Serial EEPROM

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TC9WMB4FU Datasheet, PDF (4/17 Pages) Toshiba Semiconductor – CMOS Digital Integrated Circuits Silicon Monolithic 4096-Bit (512 × 8-Bit) 2-Wire Serial EEPROM

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TC9WMB4FU

3. Acknowledge

Data is transmitted in 8-bit units. The device sends âlowâ of an acknowledge signal, by pulling SDA

during the 9th clock cycle, indicating that it has received data normally. The host releases the bus in the 9th

clock cycle to receive an acknowledge signal.

During a write operations, the device is always the receiver so that an acknowledge signal is sent each

time it has received 8-bit of data.

During a read operations, the device sends an acknowledge signal after it receives an address following a

start condition. Then, a read data is sent and releases the bus to wait for an acknowledge signal from the

master. When an acknowledge signal is detected, next address data is sent if a stop condition is not detected.

If the device does not detect an acknowledge signal, a read operations is stopped, and enters the standby

mode when a stop condition occurs subsequently.

If the device does not detect an acknowledge signal nor a stop condition, it keeps the bus released.

SCL

SDA

(input)

SDA

(output)

Start condition

tAA

tDH

Acknowledge output

Figure 3

4. Device Addressing

After a start condition occurs, 7-bit device address and a 1-bit read/write instruction code are transferred

to the device.

The first four bits are called device code, which must always be â1â, â0â, â1â,â0â. The next two bits are

called slave address and are used to select a device on the bus. The slave address is compared to the value

on the address inputs (A1 and A2). The next bit is called page address (P0). P0 on â0â selects the memory

area of the first 2k-bit (000 to 0FF) and on â1â selects the memory area of the last 2k-bit (100 to 1FF).

The least significant bit ( R/W : READ/WRITE ) indicates a read instruction when set to â1â and a write

instruction when set to â0â.

An instruction is not executed if the device address does not match the specified value.

Device address

Read/write

instruction code

Device code

Slave Page

address address

1 0 1 0 A2 A1 P0 R / W

MSD

LSB

Figure 4

2007-10-19

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