TC35273 Datasheet, PDF (6/23 Pages) Toshiba Semiconductor – MPEG-4 Audiovisual LSI

Preliminary
MPEG-4 Audiovisual Codec LSI
TC35273
Signal Name
/RESET
STANDBY
In/Out
In
In
Table 1. System Control Signals
Bit Width
1
1
Description
System Reset Input (Low Active). When the LSI is reset, the reset pin has
to be low for more than 16 clock cycles. When power on, the LSI has to be
reset after PLL locked. It takes approximately 100us until the PLL locked.
System Standby Input (High Active).
When it is high, power is not supplied to the internal logic, SRAM, and
DRAM.
“0”: Normal Operation.
“1”: Standby.
Signal Name
PLLFN
PLLDIV[2:0]
PLLAVD
PLLAVS
In/Out
In
In
In
In
Bit Width
1
3
1
1
Table 2. PLL Control Signals
Description
Reference Clock Input.
It has to be 13.00MHz to 20MHz with +/- 10% duty.
System clock frequency select. System Clock = PLLFN * N.
“000”: N=2.5.
“001”: N=3.0.
“010” : N=3.5
“011”: N=4.0.
“100”: N=4.5.
“101”: N=5:0.
“110”: N=5.5.
“111”: N=6.0.
Analog PLL Power (VDD).
Analog PLL Ground (VSS).
Signal Name
/HCS
/HWR
/HRD
HADDR[6:0]
HDAT[15:0]
HWAIT
HINT
In/Out
In
In
In
In
In/Out
Out
Out
Bit Width
1
1
1
7
16
1
1
Table 3. Host Interface
Description
Chip enable input (low active).
“0” : Chip select.
“1” : Non operation.
Write strobe (low active).
“0” : Write operation.
“1” : Non operation.
Read Strobe (low active).
“0” : Read operation.
“1” : Non operation.
Address signal.
Data signal.
Bus wait signal (low active).
“0” : Wait.
“1” : Non wait.
Interrupt signal (high active).
“0” : Non operation.
“1” : Interrupt operation.
Table 4 Video General Serial Interface
Signal Name
VGSCLK
VGSADIO
VGSBDO
In/Out
Out
In/Out
Out
Bit Width
1
1
1
TOSHIBA Confidential
6/23
Description
General I/F clock output. Please open unless this interface is used.
Input/output of serial data on port A. Open unless this interface is used.
Output of serial data on port B. Open unless this interface is used.
2000-4-27
Version 0.90