TC35273 Datasheet, PDF (4/23 Pages) Toshiba Semiconductor – MPEG-4 Audiovisual LSI

Preliminary
MPEG-4 Audiovisual Codec LSI
TC35273
1.2. System configuration.
Fig. 1 illustrates a block diagram of this LSI. Three signal processing core, peripheral interfaces,
and 12-Mbit DRAM are integrated in a single chip.
Bitstream input/output are performed via a network interface in the Mux/Demux core.
A Microphone and a speaker can be connected to a PCM interface in a speech/audio core via
external DAC and ADC.
TOSHIBA CMOS camera is connected to a camera interface via a camera DSP “TC90A50F” or
“TC90A70F”. NTSC camera is also connected via an NTSC decoder.
LCD or NTSC display is connected to an LCD interface via TOSHIBA LCD controller or an NTSC
encoder, respectively.
Host CPU is connected via a host interfaces. It downloads firmwares into the embedded DRAM
and accesses to internal registers.
MPEG-4 Video
RISC HW HW
DMA Controller
D/A
A/D
Speech/Audio
RISC HW HW
DMA Controller
Bitstream In/Out
Network Bitstream
Interface
Mux./Demux.
RISC HW HW
DMA Controller
Arbiter + DRAM Controller
12Mbit Embedded DRAM
LCD
I/F
LCDC
Cam.
I/F
Camera
DSP
Pre-
filter
Host
I/F
Host
CPU
Fig. 1 Block Diagram
TOSHIBA Confidential
4/23
Version 0.90
2000-4-27