TC35273 Datasheet, PDF (18/23 Pages) Toshiba Semiconductor – MPEG-4 Audiovisual LSI

Preliminary
MPEG-4 Audiovisual Codec LSI
TC35273
Table 14 Display Interface Timing
Parameter
Description
Min
T_CYCLE
Cycle time of DISPCLK
100
T_SETUP
Setup time of DISPHSYN and DISPVSYN
2
T_HOLD
Hold time DISPHSYN and DISPVSYN
2
T_DELAY
Delay time of DISPBLK and DISPPXL
* When system clock is 40MHz, DSPCLK has to be less than 10MHz.
Max
(T_SYSCLK*3)+15
Unit
ns
ns
ns
ns
3.5 Audio ADC&DAC Interface
Asani-kasei “AK4158” and “AK4323” are connected for external ADC and DAC, respectively.
ADOMCLK
ADSCLK
ADSDI
ADLRCLK
ADSDO
T_MCKW
T_SCKD
T_SCKW
T_SDIS
T_SDIH
T_LCKDH
T_LCKDH
T_SDOD
Fig. 13 Audio ADC&DAC Interface
TOSHIBA Confidential
18/23
Version 0.90
2000-4-27