TC35273 Datasheet, PDF (19/23 Pages) Toshiba Semiconductor – MPEG-4 Audiovisual LSI

Preliminary
MPEG-4 Audiovisual Codec LSI
TC35273
ASCLK
ALRCK
ASDTI
ASDTO
16 Clock Cycles
0 15 14 13 12 11
0 15 14 13 12 11
1 0 15 14 13
1 0 15 14 13
Rch Data
Lch Data
Fig. 14 Audio ADC&DAC Interface (Master clock output mode).
Table 15 Audio ADC&DAC Interface Timing (Master clock output mode).
Parameter
T_MCKW
T_SCKW
T_SDIS
T_SDIH
T_LCKD
T_SDOD
Description
Clock cycle period of ADOMCLK.
Duty ratio of ADOMCLK.
Clock cycle period of ADSCLK.
Delay time from ADOMCLK to ADKCLK.
Setup time of ADSDI.
Hold time of ADSDI.
Delay time from ADSCLK to ADLRLCK.
Delay time from ADSCLK to ADSDO.
Min Max
80
50+/-10
TMCKW*8
*2 TSYSCLK
*1 TSYSCLK
*4 TSYSCLK
*1 TSYSCLK
*6 TSYSCLK
Unit
ns
%
ns
ns
ns
ns
ns
ns
TOSHIBA Confidential
19/23
Version 0.90
2000-4-27