TC35273 Datasheet, PDF (1/23 Pages) Toshiba Semiconductor – MPEG-4 Audiovisual LSI

Preliminary
MPEG-4 Audiovisual Codec LSI
TC35273
TOSHIBA MPEG-4 Audiovisual LSI
TC35273
Tentative Technical Data Sheet
MPEG-4 Audiovisual LSI
Features
U TC35273 is an MPEG-4 audiovisual codec LSI
which supports 3GPP 3G-324M video telephony
system. MPEG-4 video codec with QCIF (176x144
pixel) at 15 frames/s, AMR (Adaptive Multi Rate)
speech codec, and ITU-T H.223 are executed
concurrently at around 70MHz clock rate.
U Three signal processing units, an MPEG-4 video
codec, a speech codec / audio decoder, and a
multiplex / demultiplex unit, are integrated on a
P-FBGA201-1515-0.80A5
single chip.
U A 12-Mbit embedded DRAM is integrated as a shared memory for the three signal processing
units. The embedded DRAM helps to reduce power consumption without performance
degradation.
U Each signal processing unit consists of a 16-bit RISC processor and dedicated hardware
accelerators so as to bring programmability, high performance and low power consumption.
U Firmware programs for the RISCs are downloaded into the embedded DRAM before starting
operation. Various applications are performed by choosing an appropriate firmware.
U General host interface are adopted in order to support various host CPU.
U 2.5x to 6x of PLL is integrated on the chip for easy system integration.
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TOSHIBA Confidential
1/23
2000-4-27
Version 0.90