TC55VEM316AXBN40 Datasheet, PDF(4/14 Page) Toshiba Semiconductor – TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

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TC55VEM316AXBN40 Datasheet, PDF (4/14 Pages) Toshiba Semiconductor – TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

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TC55VEM316AXBN40,55

DC CHARACTERISTICS (Ta = â40Â° to 85Â°C, VDD = 2.3 to 3.6 V)

SYMBOL PARAMETER

TEST CONDITION

IIL

Input Leakage

Current

VIN = 0 V~VDD

IOH

Output High Current VOH = VDD â 0.5 V

IOL

Output Low Current VOL = 0.4 V

ILO

Output Leakage

Current

CE1 = VIH or CE2 = VIL or LB = UB = VIH or

R/W = VIL or OE = VIH, VOUT = 0 V~VDD

IDDO1

IDDO2

Operating Current

CE1 = VIL and CE2 = VIH and

R/W = VIH, LB = UB = VIL,

IOUT = 0 mA

Other Input = VIH/VIL

CE1 = 0.2 V and CE2 = VDD â 0.2 V and

R/W = VDD â 0.2 V, LB = UB = 0.2 V,

IOUT = 0 mA

Other Input = VDD â 0.2 V/0.2 V

MIN

tcycle

1 Âµs

MIN

1 Âµs

MIN TYP MAX UNIT

ï£§ ï£§ Â±1.0 ÂµA

â0.5 ï£§

2.1 ï£§

ï£§ mA

ï£§ ï£§ Â±1.0 ÂµA

ï£§ ï£§ 35

ï£§ï£§ 8

ï£§ ï£§ 30

ï£§ï£§ 3

IDDS1

IDDS2

Standby Current

1) CE1 = VIH or CE2 = VIL

2) LB = UB = VIH

ï£§ ï£§ 1 mA

CE1

= VDD â 0.2 V, CE2 = 0.2 V

VDD =

3.3VÂ± 0.3 V

Ta = â40~85Â°C

ï£§

2) CE2 = 0.2 V

Ta = 25Â°C

ï£§ 0.7 ï£§ ÂµA

3) LB = UB = VDD â 0.2 V,

VDD =3.0 V Ta = â40~40Â°C ï£§ ï£§ 2

CE1 = 0.2 V, CE2 = VDD â 0.2 V

Ta = â40~85Â°C ï£§ ï£§ 5

CAPACITANCE (Ta = 25Â°C, f = 1 MHz)

SYMBOL

PARAMETER

TEST CONDITION

CIN

COUT

Input Capacitance

Output Capacitance

VIN = GND

VOUT = GND

Note: This parameter is periodically sampled and is not 100% tested.

MAX

UNIT

2002-07-23 4/14

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