TC55VEM316AXBN40 Datasheet, PDF (10/14 Pages) Toshiba Semiconductor – TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

WRITE CYCLE 4 (UB, LB CONTROLLED) ^{(See Note 4)}
TC55VEM316AXBN40,55
Address
A0~A18
R/W
CE1
CE2
UB , LB
D_OUT
I/O1~16
D_IN
I/O1~16
t_WC
t_AS
t_WP
t_WR
t_CW
t_CW
t_BW
Hi-Z
t_BE t_ODW
t_COE
(See Note 5)
Hi-Z
t_DS
t_DH
VALID DATA IN
Note:
(1)
(2)
(3)
(4)
(5)
R/W remains HIGH for the read cycle.
If CE1 (or UB or LB ) goes LOW(or CE2 goes HIGH) coincident with or after R/W goes LOW, the
outputs will remain at high impedance.
If CE1 (or UB or LB ) goes HIGH(or CE2 goes LOW) coincident with or before R/W goes HIGH, the
outputs will remain at high impedance.
If OE is HIGH during the write cycle, the outputs will remain at high impedance.
Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be
applied.
2002-07-23 10/14