TC55VEM316AXBN40 Datasheet, PDF (1/14 Pages) Toshiba Semiconductor – TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

TC55VEM316AXBN40,55
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
524,288-WORD BY 16-BIT FULL CMOS STATIC RAM
DESCRIPTION
The TC55VEM316AXBN is a 8,388,608-bit static random access memory (SRAM) organized as 524,288 words by
16 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.3 to
3.6 V power supply. Advanced circuit technology provides both high speed and low power at an operating current of
3 mA/MHz and a minimum cycle time of 40 ns. It is automatically placed in low-power mode at 0.7 µA standby
current (at VDD = 3 V, Ta = 25°C, typical) when chip enable ( CE1 ) is asserted high or (CE2) is asserted low. There
are three control inputs. CE1 and CE2 are used to select the device and for data retention control, and output
enable ( OE ) provides fast memory access. Data byte control pin ( LB , UB ) provides lower and upper byte access.
This device is well suited to various microprocessor system applications where high speed, low power and battery
backup are required. And, with a guaranteed operating extreme temperature range of −40° to 85°C, the
TC55VEM316AXBN can be used in environments exhibiting extreme temperature conditions. The
TC55VEM316AXBN is available in a plastic 48-ball BGA.
FEATURES
• Low-power dissipation
Operating: 9 mW/MHz (typical)
• Single power supply voltage of 2.3 to 3.6 V
• Power down features using CE1 and CE2
• Data retention supply voltage of 1.5 to 3.6 V
• Direct TTL compatibility for all inputs and outputs
• Wide operating temperature range of −40° to 85°C
• Standby Current (maximum):
3.6 V
3.0 V
10 µA
5 µA
• Access Times:
TC55VEM316AXBN
40
55
Access Time
40 ns
55 ns
CE1 Access Time
40 ns
55 ns
CE2 Access Time
40 ns
55 ns
OE Access Time
25 ns
• Package:
P-TFBGA48-0811-0.75BZ (Weight:
30 ns
g typ)
PIN ASSIGNMENT (TOP VIEW)
48 PIN BGA
1
2
3
4
5
6
A LB OE A0 A1 A2 CE2
B I/O9 UB A3 A4 CE1 I/O1
C I/O10 I/O11 A5 A6 I/O2 I/O3
D V_SS I/O12 A17 A7 I/O4 V_DD
E V_DD I/O13 OP A16 I/O5 V_SS
F I/O15 I/O14 A14 A15 I/O6 I/O7
G I/O16 NC A12 A13 R/W I/O8
H A18 A8 A9 A10 A11 NC
PIN NAMES
A0~A18
CE1 , CE2
R/W
OE
LB , UB
I/O1~I/O16
V_DD
GND
NC
OP*
Address Inputs
Chip Enable
Read/Write Control
Output Enable
Data Byte Control
Data Inputs/Outputs
Power
Ground
No Connection
Option
*: OP pin must be open or connected to GND.
2002-07-23 1/14