TC55VEM316AXBN40 Datasheet, PDF (12/14 Pages) Toshiba Semiconductor – TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

TC55VEM316AXBN40,55
Note:
(1)
(2)
(3)
(4)
(5)
In CE1 controlled data retention mode, minimum standby current mode is entered when CE2 ≤ 0.2 V or
CE2 ≥ VDD − 0.2 V.
When CE1 is operating at the VIH(min.) level, the operating current is given by IDDS1 during the
transition of VDD from 2.3(2.7) to 2.2V(2.4 V).
In CE2 controlled data retention mode, minimum standby current mode is entered when CE2 ≤ 0.2 V.
In UB (or LB ) controlled data retention mode, minimum standby current mode is entered when CE1
≤ 0.2 V or CE1 ≥ VDD − 0.2 V, CE2 ≤ 0.2 V or CE2 ≥ VDD − 0.2 V.
When CE1 is operating at the VIH(min.) level, the operating current is given by IDDS1 during the
transition of VDD from 2.3(2.7) to 2.2V(2.4 V).
2002-07-23 12/14