SSM6L13TU_10 Datasheet, PDF (3/8 Pages) Toshiba Semiconductor – TOSHIBA Field-Effect Transistor Silicon P / N Channel MOS Type

Q1 Switching Time Test Circuit
(a) Test Circuit
2.5 V
IN
0
10 μs
V_DD = 10 V
R_G = 4.7 Ω
Duty ≤ 1%
V_IN: t_r, t_f < 5 ns
Common Source
Ta = 25 °C
OUT
V_DD
Q2 Switching Time Test Circuit
(a) Test Circuit
0
IN
− 2.5 V
10 μs
V_DD = - 10 V
R_G = 4.7 Ω
Duty ≤ 1 %
V_IN: t_r, t_f < 5 ns
Common Source
Ta = 25 °C
OUT
R_L
V_DD
SSM6L13TU
(b) V_IN
(c) V_OUT
2.5 V
0V
V_DD
V_{DS (ON)}
10 %
90 %
90 %
10 %
t_r
t_f
t_on
t_off
(b) V_IN
0V
(c) V_OUT
−2.5 V
V_{DS (ON)}
V_DD
90 %
10 %
90 %
10 %
t_r
t_f
t_on
t_off
Q1 Precaution
V_th can be expressed as the voltage between gate and source when the low operating current value is I_D= 1 mA for
this product. For normal switching operation, V_{GS (on)} requires a higher voltage than V_th, and V_{GS (off)} requires a lower
voltage than V_th.
(The relationship can be established as follows: V_{GS (off)} < V_th < V_{GS (on).} )
Take this into consideration when using the device.
Q2 Precaution
V_th can be expressed as the voltage between gate and source when the low operating current value is I_D= − 1 mA for
this product. For normal switching operation, V_{GS (on)} requires a higher voltage than V_th, and V_{GS (off)} requires a lower
voltage than V_th.
(The relationship can be established as follows: V_{GS (off)} < V_th < V_{GS (on).} )
Take this into consideration when using the device.
Handling Precaution
When handling individual devices that are not yet mounted on a circuit board, make sure that the environment is
protected against electrostatic discharge. Operators should wear antistatic clothing, and containers and other objects that
come into direct contact with devices should be made of antistatic materials.
Thermal resistance R_{th (ch-a)} and Power dissipation P_D vary depending on board material, board area, board thickness
and pad area. When using this device, please take heat dissipation into consideration.
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2010-07-10