LM3S9B95-IQC80-C3 Datasheet, PDF (990/1401 Pages) Texas Instruments – Stellaris® LM3S9B95 Microcontroller

NRND: Not recommended for new designs.
Universal Serial Bus (USB) Controller
19.3.4
USB controller begins this reset sequence automatically to ensure that RESET is started as required
within 1 ms of the A device connecting its pull-up resistor. The main processor should wait at least
20 ms, then clear the RESET bit and enumerate the A device.
When the USB OTG controller B device has finished using the bus, the USB controller goes into
SUSPEND mode by setting the SUSPEND bit in the USBPOWER register. The A device detects this
and either terminates the session or reverts to Host mode. If the A device is USB OTG controller,
it generates a Disconnect interrupt.
DMA Operation
The USB peripheral provides an interface connected to the μDMA controller with separate channels
for 3 transmit endpoints and 3 receive endpoints. Software selects which endpoints to service with
the μDMA channels using the USB DMA Select (USBDMASEL) register. The μDMA operation of
the USB is enabled through the USBTXCSRHn and USBRXCSRHn registers, for the TX and RX
channels respectively. When μDMA operation is enabled, the USB asserts a μDMA request on the
enabled receive or transmit channel when the associated FIFO can transfer data. When either FIFO
can transfer data, the burst request for that channel is asserted. The μDMA channel must be
configured to operate in Basic mode, and the size of the μDMA transfer must be restricted to whole
multiples of the size of the USB FIFO. Both read and write transfers of the USB FIFOs using μDMA
must be configured in this manner. For example, if the USB endpoint is configured with a FIFO size
of 64 bytes, the μDMA channel can be used to transfer 64 bytes to or from the endpoint FIFO. If the
number of bytes to transfer is less than 64, then a programmed I/O method must be used to copy
the data to or from the FIFO.
If the DMAMOD bit in the USBTXCSRHn/USBRXCSRHn register is clear, an interrupt is generated
after every packet is transferred, but the μDMA continues transferring data. If the DMAMOD bit is set,
an interrupt is generated only when the entire μDMA transfer is complete. The interrupt occurs on
the USB interrupt vector. Therefore, if interrupts are used for USB operation and the μDMA is
enabled, the USB interrupt handler must be designed to handle the μDMA completion interrupt.
Care must be taken when using the μDMA to unload the receive FIFO as data is read from the
receive FIFO in 4 byte chunks regardless of value of the MAXLOAD field in the USBRXCSRHn
register. The RXRDY bit is cleared as follows.
Table 19-3. Remainder (MAXLOAD/4)
Value
0
1
2
3
Description
MAXLOAD = 64 bytes
MAXLOAD = 61 bytes
MAXLOAD = 62 bytes
MAXLOAD = 63 bytes
Table 19-4. Actual Bytes Read
Value
0
1
2
3
Description
MAXLOAD
MAXLOAD+3
MAXLOAD+2
MAXLOAD+1
990
October 05, 2012
Texas Instruments-Production Data