LM3S9B95-IQC80-C3 Datasheet, PDF (16/1401 Pages) Texas Instruments – Stellaris® LM3S9B95 Microcontroller

Table of Contents
NRND: Not recommended for new designs.
List of Tables
Table 1.
Table 2.
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
Table 2-5.
Table 2-6.
Table 2-7.
Table 2-8.
Table 2-9.
Table 2-10.
Table 2-11.
Table 2-12.
Table 2-13.
Table 3-1.
Table 3-2.
Table 3-3.
Table 3-4.
Table 3-5.
Table 3-6.
Table 3-7.
Table 3-8.
Table 3-9.
Table 4-1.
Table 4-2.
Table 4-3.
Table 4-4.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 5-5.
Table 5-6.
Table 5-7.
Table 5-8.
Table 5-9.
Table 6-1.
Table 6-2.
Table 6-3.
Table 7-1.
Table 7-2.
Table 7-3.
Table 7-4.
Table 7-5.
Table 7-6.
Revision History .................................................................................................. 42
Documentation Conventions ................................................................................ 54
Summary of Processor Mode, Privilege Level, and Stack Use ................................ 84
Processor Register Map ....................................................................................... 85
PSR Register Combinations ................................................................................. 90
Memory Map ....................................................................................................... 98
Memory Access Behavior ................................................................................... 101
SRAM Memory Bit-Banding Regions ................................................................... 103
Peripheral Memory Bit-Banding Regions ............................................................. 103
Exception Types ................................................................................................ 109
Interrupts .......................................................................................................... 110
Exception Return Behavior ................................................................................. 115
Faults ............................................................................................................... 116
Fault Status and Fault Address Registers ............................................................ 117
Cortex-M3 Instruction Summary ......................................................................... 119
Core Peripheral Register Regions ....................................................................... 122
Memory Attributes Summary .............................................................................. 125
TEX, S, C, and B Bit Field Encoding ................................................................... 128
Cache Policy for Memory Attribute Encoding ....................................................... 129
AP Bit Field Encoding ........................................................................................ 129
Memory Region Attributes for Stellaris Microcontrollers ........................................ 129
Peripherals Register Map ................................................................................... 130
Interrupt Priority Levels ...................................................................................... 157
Example SIZE Field Values ................................................................................ 185
JTAG_SWD_SWO Signals (100LQFP) ................................................................ 189
JTAG_SWD_SWO Signals (108BGA) ................................................................. 190
JTAG Port Pins State after Power-On Reset or RST assertion .............................. 191
JTAG Instruction Register Commands ................................................................. 196
System Control & Clocks Signals (100LQFP) ...................................................... 200
System Control & Clocks Signals (108BGA) ........................................................ 200
Reset Sources ................................................................................................... 201
Clock Source Options ........................................................................................ 208
Possible System Clock Frequencies Using the SYSDIV Field ............................... 210
Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 210
Examples of Possible System Clock Frequencies with DIV400=1 ......................... 211
System Control Register Map ............................................................................. 215
RCC2 Fields that Override RCC Fields ............................................................... 237
Flash Memory Protection Policy Combinations .................................................... 312
User-Programmable Flash Memory Resident Registers ....................................... 316
Flash Register Map ............................................................................................ 316
μDMA Channel Assignments .............................................................................. 347
Request Type Support ....................................................................................... 349
Control Structure Memory Map ........................................................................... 350
Channel Control Structure .................................................................................. 350
μDMA Read Example: 8-Bit Peripheral ................................................................ 359
μDMA Interrupt Assignments .............................................................................. 360
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October 05, 2012
Texas Instruments-Production Data