LM3S9B95-IQC80-C3 Datasheet, PDF (68/1401 Pages) Texas Instruments – Stellaris® LM3S9B95 Microcontroller

Architectural Overview
NRND: Not recommended for new designs.
1.3.4.7
■ Separate transmit and receive FIFOs, each 16 bits wide and 8 locations deep
■ Programmable data frame size from 4 to 16 bits
■ Internal loopback test mode for diagnostic/debug testing
■ Standard FIFO-based interrupts and End-of-Transmission interrupt
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive
– Receive single request asserted when data is in the FIFO; burst request asserted when FIFO
contains 4 entries
– Transmit single request asserted when there is space in the FIFO; burst request asserted
when FIFO contains 4 entries
Inter-Integrated Circuit Sound (I²S) Interface (see page 827)
The I²S interface is a configurable serial audio core that contains a transmit module and a receive
module. The module is configurable for the I²S as well as Left-Justified and Right-Justified serial
audio formats. Data can be in one of four modes: Stereo, Mono, Compact 16-bit Stereo and Compact
8-Bit Stereo.
The transmit and receive modules each have an 8-entry audio-sample FIFO. An audio sample can
consist of a Left and Right Stereo sample, a Mono sample, or a Left and Right Compact Stereo
sample. In Compact 16-Bit Stereo, each FIFO entry contains both the 16-bit left and 16-bit right
samples, allowing efficient data transfers and requiring less memory space. In Compact 8-bit Stereo,
each FIFO entry contains an 8-bit left and an 8-bit right sample, reducing memory requirements
further.
Both the transmitter and receiver are capable of being a master or a slave.
The Stellaris I²S interface has the following features:
■ Configurable audio format supporting I²S, Left-justification, and Right-justification
■ Configurable sample size from 8 to 32 bits
■ Mono and Stereo support
■ 8-, 16-, and 32-bit FIFO interface for packing memory
■ Independent transmit and receive 8-entry FIFOs
■ Configurable FIFO-level interrupt and µDMA requests
■ Independent transmit and receive MCLK direction control
■ Transmit and receive internal MCLK sources
■ Independent transmit and receive control for serial clock and word select
■ MCLK and SCLK can be independently set to master or slave
■ Configurable transmit zero or last sample when FIFO empty
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October 05, 2012
Texas Instruments-Production Data