LM3S9B95-IQC80-C3 Datasheet, PDF (23/1401 Pages) Texas Instruments – Stellaris® LM3S9B95 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S9B95 Microcontroller
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Device Capabilities 0 (DC0), offset 0x008 ........................................................................ 248
Device Capabilities 1 (DC1), offset 0x010 ........................................................................ 249
Device Capabilities 2 (DC2), offset 0x014 ........................................................................ 252
Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 254
Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 257
Device Capabilities 5 (DC5), offset 0x020 ........................................................................ 259
Device Capabilities 6 (DC6), offset 0x024 ........................................................................ 261
Device Capabilities 7 (DC7), offset 0x028 ........................................................................ 262
Device Capabilities 8 ADC Channels (DC8), offset 0x02C ................................................ 266
Device Capabilities 9 ADC Digital Comparators (DC9), offset 0x190 ................................. 269
Non-Volatile Memory Information (NVMSTAT), offset 0x1A0 ............................................. 271
Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 272
Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 275
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 278
Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 280
Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 284
Deep-Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 288
Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 292
Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 295
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 298
Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 301
Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 303
Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 306
Internal Memory ........................................................................................................................... 308
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 318
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 319
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 320
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 323
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 324
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 325
Register 7: Flash Memory Control 2 (FMC2), offset 0x020 ................................................................. 326
Register 8: Flash Write Buffer Valid (FWBVAL), offset 0x030 ............................................................. 327
Register 9: Flash Control (FCTL), offset 0x0F8 ................................................................................. 328
Register 10: Flash Write Buffer n (FWBn), offset 0x100 - 0x17C .......................................................... 329
Register 11: ROM Control (RMCTL), offset 0x0F0 .............................................................................. 330
Register 12: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 331
Register 13: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 332
Register 14: Boot Configuration (BOOTCFG), offset 0x1D0 ................................................................. 333
Register 15: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 335
Register 16: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 336
Register 17: User Register 2 (USER_REG2), offset 0x1E8 .................................................................. 337
Register 18: User Register 3 (USER_REG3), offset 0x1EC ................................................................. 338
Register 19: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 339
Register 20: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 340
Register 21: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 341
Register 22: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 342
Register 23: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 343
Register 24: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 344
October 05, 2012
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