LM3S9B95-IQC80-C3 Datasheet, PDF (493/1401 Pages) Texas Instruments – Stellaris® LM3S9B95 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S9B95 Microcontroller
Register 3: EPI SDRAM Configuration (EPISDRAMCFG), offset 0x010
Important: The MODE field in the EPICFG register determines which configuration register is
accessed for offsets 0x010 and 0x014.
To access EPISDRAMCFG, the MODE field must be 0x1.
The SDRAM Configuration register is used to specify several parameters for the SDRAM controller.
Note that this register is reset when the MODE field in the EPICFG register is changed. If another
mode is selected and the SDRAM mode is selected again, the values must be reinitialized.
The SDRAM interface is designed to interface to x16 SDR SDRAMs of 64 MHz or higher, with the
address and data pins overlapped (wire ORed on the board). See Table 9-3 on page 466 for pin
assignments.
EPI SDRAM Configuration (EPISDRAMCFG)
Base 0x400D.0000
Offset 0x010
Type R/W, reset 0x82EE.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
FREQ
reserved
RFSH
Type R/W
R/W
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1
0
0
0
0
0
1
0
1
1
1
0
1
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
SLEEP
reserved
SIZE
Type RO
RO
RO
RO
RO
RO
R/W
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:30
Name
FREQ
Type
R/W
Reset
0x2
Description
EPI Frequency Range
This field configures the frequency range used for delay references by
internal counters. This EPI frequency is the system frequency with the
divider programmed by the COUNT0 bit in the EPIBAUDn register bit.
This field affects the power up, precharge, and auto refresh delays. This
field does not affect the refresh counting, which is configured separately
using the RFSH field (and is based on system clock rate and number of
rows per bank). The ranges are:
Value Description
0x0 0 - 15 MHz
0x1 15 - 30 MHz
0x2 30 - 50 MHz
0x3 50 - 100 MHz
29:27
26:16
reserved
RFSH
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
0x2EE Refresh Counter
This field contains the refresh counter in system clocks. The reset value
of 0x2EE provides a refresh period of 64 ms when using a 50 MHz clock.
October 05, 2012
493
Texas Instruments-Production Data