LM3S5R31 Datasheet, PDF (966/1275 Pages) Texas Instruments – Stellaris® LM3S5R31 Microcontroller

Universal Serial Bus (USB) Controller
Register 12: USB FIFO Endpoint 0 (USBFIFO0), offset 0x020
Register 13: USB FIFO Endpoint 1 (USBFIFO1), offset 0x024
Register 14: USB FIFO Endpoint 2 (USBFIFO2), offset 0x028
Register 15: USB FIFO Endpoint 3 (USBFIFO3), offset 0x02C
Register 16: USB FIFO Endpoint 4 (USBFIFO4), offset 0x030
Register 17: USB FIFO Endpoint 5 (USBFIFO5), offset 0x034
Register 18: USB FIFO Endpoint 6 (USBFIFO6), offset 0x038
Register 19: USB FIFO Endpoint 7 (USBFIFO7), offset 0x03C
Register 20: USB FIFO Endpoint 8 (USBFIFO8), offset 0x040
Register 21: USB FIFO Endpoint 9 (USBFIFO9), offset 0x044
Register 22: USB FIFO Endpoint 10 (USBFIFO10), offset 0x048
Register 23: USB FIFO Endpoint 11 (USBFIFO11), offset 0x04C
Register 24: USB FIFO Endpoint 12 (USBFIFO12), offset 0x050
Register 25: USB FIFO Endpoint 13 (USBFIFO13), offset 0x054
Register 26: USB FIFO Endpoint 14 (USBFIFO14), offset 0x058
Register 27: USB FIFO Endpoint 15 (USBFIFO15), offset 0x05C
Important: This register is read-sensitive. See the register description for details.
These 32-bit registers provide an address for CPU access to the FIFOs for each endpoint. Writing
to these addresses loads data into the Transmit FIFO for the corresponding endpoint. Reading from
these addresses unloads data from the Receive FIFO for the corresponding endpoint.
Transfers to and from FIFOs may be 8-bit, 16-bit or 32-bit as required, and any combination of
accesses is allowed provided the data accessed is contiguous. All transfers associated with one
packet must be of the same width so that the data is consistently byte-, halfword- or word-aligned.
However, the last transfer may contain fewer bytes than the previous transfers in order to complete
an odd-byte or odd-word transfer.
Depending on the size of the FIFO and the expected maximum packet size, the FIFOs support
either single-packet or double-packet buffering (see the section called “Single-Packet
Buffering” on page 938). Burst writing of multiple packets is not supported as flags must be set after
each packet is written.
Following a STALL response or a transmit error on endpoint 1–15, the associated FIFO is completely
flushed.
966
January 20, 2012
Texas Instruments-Production Data