LM3S5R31 Datasheet, PDF (25/1275 Pages) Texas Instruments – Stellaris® LM3S5R31 Microcontroller

Stellaris^® LM3S5R31 Microcontroller
Register 17:
Register 18:
Register 19:
Register 20:
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Register 30:
Register 31:
Register 32:
EPI Status (EPISTAT), offset 0x060 ................................................................................ 539
EPI Read FIFO Count (EPIRFIFOCNT), offset 0x06C ...................................................... 541
EPI Read FIFO (EPIREADFIFO), offset 0x070 ................................................................ 542
EPI Read FIFO Alias 1 (EPIREADFIFO1), offset 0x074 .................................................... 542
EPI Read FIFO Alias 2 (EPIREADFIFO2), offset 0x078 .................................................... 542
EPI Read FIFO Alias 3 (EPIREADFIFO3), offset 0x07C ................................................... 542
EPI Read FIFO Alias 4 (EPIREADFIFO4), offset 0x080 .................................................... 542
EPI Read FIFO Alias 5 (EPIREADFIFO5), offset 0x084 .................................................... 542
EPI Read FIFO Alias 6 (EPIREADFIFO6), offset 0x088 .................................................... 542
EPI Read FIFO Alias 7 (EPIREADFIFO7), offset 0x08C ................................................... 542
EPI FIFO Level Selects (EPIFIFOLVL), offset 0x200 ........................................................ 543
EPI Write FIFO Count (EPIWFIFOCNT), offset 0x204 ...................................................... 545
EPI Interrupt Mask (EPIIM), offset 0x210 ......................................................................... 546
EPI Raw Interrupt Status (EPIRIS), offset 0x214 .............................................................. 547
EPI Masked Interrupt Status (EPIMIS), offset 0x218 ........................................................ 549
EPI Error and Interrupt Status and Clear (EPIEISC), offset 0x21C .................................... 550
General-Purpose Timers ............................................................................................................. 552
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 569
Register 2: GPTM Timer A Mode (GPTMTAMR), offset 0x004 ........................................................... 570
Register 3: GPTM Timer B Mode (GPTMTBMR), offset 0x008 ........................................................... 572
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 574
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 577
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 579
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 582
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 585
Register 9: GPTM Timer A Interval Load (GPTMTAILR), offset 0x028 ................................................ 587
Register 10: GPTM Timer B Interval Load (GPTMTBILR), offset 0x02C ................................................ 588
Register 11: GPTM Timer A Match (GPTMTAMATCHR), offset 0x030 .................................................. 589
Register 12: GPTM Timer B Match (GPTMTBMATCHR), offset 0x034 ................................................. 590
Register 13: GPTM Timer A Prescale (GPTMTAPR), offset 0x038 ....................................................... 591
Register 14: GPTM Timer B Prescale (GPTMTBPR), offset 0x03C ...................................................... 592
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 593
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 594
Register 17: GPTM Timer A (GPTMTAR), offset 0x048 ....................................................................... 595
Register 18: GPTM Timer B (GPTMTBR), offset 0x04C ....................................................................... 596
Register 19: GPTM Timer A Value (GPTMTAV), offset 0x050 ............................................................... 597
Register 20: GPTM Timer B Value (GPTMTBV), offset 0x054 .............................................................. 598
Watchdog Timers ......................................................................................................................... 599
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 603
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 604
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 605
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 607
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 608
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 609
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 610
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 611
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 612
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 613
January 20, 2012
25
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