LM3S5R31 Datasheet, PDF (853/1275 Pages) Texas Instruments – Stellaris® LM3S5R31 Microcontroller

Stellaris^® LM3S5R31 Microcontroller
are configurable with the SSZ and SDSZ bits in the I²S Transmit Module Configuration (I2STXCFG)
register. The sample size is the number of bits of data being transmitted, and the system data size
is the number of I2S0TXSCK transitions between the word select transitions. The system data size
must be large enough to accommodate the maximum sample size. In Mono mode, the sample data
is repeated in both the left and right channels. When the FIFO is empty, the user may select either
transmission of zeros or of the last sample. The serial encoder is enabled using the TXEN bit in the
I²S Module Configuration (I2SCFG) register.
17.3.1.2
FIFO Operation
The transmit FIFO stores eight Mono samples or eight Stereo sample-pairs of data and is accessed
through the I²S Transmit FIFO Data (I2STXFIFO) register. The FIFO interface for the audio data
is different based on the Write mode, defined by the I²S Transmit FIFO Configuration
(I2STXFIFOCFG) Compact Stereo Sample Size bit (CSS) and the I2STXCFG Write Mode field (WM).
All data samples are MSB-aligned. Table 17-3 on page 853 defines the interface for each Write mode.
Stereo samples are written first left then right. The next sample (right or left) to be written is indicated
by the LRS bit in the I2STXFIFOCFG register.
Table 17-3. I²S Transmit FIFO Interface
WM field in
I2STXCFG
0x0
0x1
0x1
0x2
CSS bit in Write Mode
I2STXFIFOCFG
don't care Stereo
0
Compact Stereo - 16 bit
Sample Width
8-32 bits
8-16 bits
1
don't care
Compact Stereo - 8 bit
Mono
8 bits
8-32 bits
Samples per
FIFO Write
Data Alignment
1
MSB
2
MSB Right [31:16], Left
[15:0]
2
Right [15:8], Left[7:0]
1
MSB
The number of samples in the transmit FIFO can be read using the I²S Transmit FIFO Level
(I2STXLEV) register. The value ranges from 0 to 16. Stereo and compact stereo sample pairs are
counted as two. The mono samples also increment the count by two, therefore, four mono samples
will have a count of eight.
17.3.1.3
Clock Control
The transmitter MCLK and SCLK can be independently programmed to be the master or slave. The
transmitter is programmed to be the master or slave of the SCLK using the MSL bit in the I2STXCFG
register. When the transmitter is the master, the I2S0TXSCK frequency is the specified I2S0TXMCLK
divided by four. The I2S0TXSCK may be inverted using the SCP bit in the I2STXCFG register.
The transmitter can also be the master or slave of the MCLK. When the transmitter is the master,
the PLL must be active and a fractional clock divider must be programmed. See page 241 for the
setup for the master I2S0TXMCLK source. An external transmit I2S0TXMCLK does not require the
use of the PLL and is selected using the TXSLV bit in the I2SCFG register.
The following tables show combinations of the TXINT and TXFRAC bits in the I²S MCLK
Configuration (I2SMCLKCFG) register that provide MCLK frequencies within acceptable error
limits. In the table, Fs is the sampling frequency in kHz and possible crystal frequencies are shown
in MHz across the top row of the table. The words "not supported" in the table mean that it is not
possible to obtain the specified sampling frequencies with the specified crystal frequency within the
error tolerance of 0.3%. The values in the table are based on the following values:
MCLK = Fs × 256
PLL = 400 MHz
January 20, 2012
853
Texas Instruments-Production Data