LM3S5R31 Datasheet, PDF (884/1275 Pages) Texas Instruments – Stellaris® LM3S5R31 Microcontroller

Inter-Integrated Circuit Sound (I²S) Interface
Register 17: I²S Interrupt Clear (I2SIC), offset 0xC1C
Writing a 1 to a bit in this register clears the corresponding interrupt.
I2S Interrupt Clear (I2SIC)
Base 0x4005.4000
Offset 0xC1C
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
RXREIC
reserved
TXWEIC reserved
Type WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:6
5
4:2
1
0
Name
reserved
RXREIC
reserved
TXWEIC
reserved
Type
WO
WO
WO
WO
WO
Reset Description
0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
Receive FIFO Read Error
Writing a 1 to this bit clears the RXRERIS bit in the I2CRIS register and
the RXREMIS bit in the I2CMIS register.
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
Transmit FIFO Write Error
Writing a 1 to this bit clears the TXWERIS bit in the I2CRIS register and
the TXWEMIS bit in the I2CMIS register.
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
884
January 20, 2012
Texas Instruments-Production Data