LM3S5R31 Datasheet, PDF (496/1275 Pages) Texas Instruments – Stellaris® LM3S5R31 Microcontroller

External Peripheral Interface (EPI)
10.4.2.2
SRAM support
Figure 10-5 on page 496 shows how to connect the EPI signals to a 16-bit SRAM and a 16-bit Flash
memory with muxed address and memory using byte selects and dual chip selects with ALE. This
schematic is just an example of how to connect the signals; timing and loading have not been
analyzed. In addition, not all bypass capacitors are shown.
Figure 10-5. Example Schematic for Muxed Host-Bus 16 Mode
EPI_16_BUS
EPI0
EPI1
EPI2
EPI3
EPI4
EPI5
EPI6
EPI7
EPI8
EPI9
EPI10
EPI11
EPI12
EPI13
EPI14
EPI15
EPI30
+3.3V
GND
47
1D1
46
1D2
44
1D3
43
1D4
41
1D5
40
1D6
38
1D7
37
1D8
36
2D1
35
2D2
33
2D3
32
2D4
30
2D5
29
2D6
27
2D7
26
2D8
25
2LE
48
1LE
1
1OE
24
2OE
7
VCC
18
VCC
31
VCC
42
VCC
U1
2
1Q1
3
1Q2
5
1Q3
6
1Q4
8
1Q5
9
1Q6
11
1Q7
12
1Q8
13
2Q1
14
2Q2
16
2Q3
17
2Q4
19
2Q5
20
2Q6
22
2Q7
23
2Q8
4
GND
10
GND
15
GND
21
GND
28
GND
34
GND
39
GND
45
GND
74X16373
A[0:15]
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
GND
EPI_16_BUS
EPI16
EPI17
A[0:15]
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
U2
5
A0
4
A1
3
A2
2
A3
1
A4
44
A5
43
A6
42
A7
27
A8
26
A9
25
A10
24
A11
23
A12
22
A13
21
A14
20
A15
19
A16
18
A17
7
I/O0
8
I/O1
9
I/O2
10
I/O3
13
I/O4
14
I/O5
15
I/O6
16
I/O7
29
I/O8
30
I/O9
31
I/O10
32
I/O11
35
I/O12
36
I/O13
37
I/O14
38
I/O15
28
NC
+3.3V
11
VCC
33
VCC
17
WE
6
CE
41
OE
12
VSS
34
VSS
40
BHE
39
BLE
GND
CY62147
EPI_16_BUS
EPI0
EPI1
EPI2
EPI3
EPI4
EPI5
EPI6
EPI7
EPI8
EPI9
EPI10
EPI11
EPI12
EPI13
EPI14
EPI15
EPI29
EPI26
EPI28
EPI25
EPI24
EPI_16_BUS
A[0:15]
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
EPI16
EPI17
EPI18
EPI_16_BUS
U3
25
A0
24
A1
23
A2
22
A3
21
A4
20
A5
19
A6
18
A7
8
A8
7
A9
6
A10
5
A11
4
A12
3
A13
2
A14
1
A15
48
A16
17
A17
16
A18
9
NC
10
NC
12
NC
13
NC
14
NC
15
NC
47
NC
29
DQ0
31
DQ1
33
DQ2
35
DQ3
38
DQ4
40
DQ5
42
DQ6
44
DQ7
30
DQ8
32
DQ9
34
DQ10
36
DQ11
39
DQ12
41
DQ13
43
DQ14
45
DQ15
11
WE
28
OE
26
CE
+3.3V
37
VDD
46
VSS
27
VSS
EPI0
EPI1
EPI2
EPI3
EPI4
EPI5
EPI6
EPI7
EPI8
EPI9
EPI10
EPI11
EPI12
EPI13
EPI14
EPI15
EPI29
EPI28
EPI27
SST39VF800A
GND
10.4.2.3
496
Speed of Transactions
The COUNT0 field in the EPIBAUD register must be configured to set the main transaction rate
based on what the slave device can support (including wiring considerations). The main control
DESIGNER
REVISION
DATE
???
?REV?
1/6/2011
TEXAS INSTRUMENTS
PROJECT
STELLARIS ^R MICROCONTROLLERS
?PROJECT NAME?
108 WILD BASIN ROAD, SUITE 350
JanuAaUryST2IN0T, X2, 07187246
D_TES_eC_xRI_aP_sTIO_InN _{struments-Production Data}
www.ti.com/stellaris
?DESC1?
?DESC2?
FILENAME
epi16_example.sch
PART NO.
?PART NUMBER?
SHEET
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