TM4C129XNCZAD Datasheet, PDF (959/2191 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C129XNCZAD Microcontroller
Bit/Field
7:6
5:4
3:2
Name
WRWS
RDWS
reserved
Type
RW
RW
RO
Reset
0x0
0x0
0x0
Description
CS3n Write Wait States
This field adds wait states to the data phase of CS3n accesses (the
address phase is not affected). The effect is to delay the rising edge of
WRn (or the falling edge of WR). Each wait state adds 2 EPI clock cycles
to the access time. The WRWSM bit in the EPIHB8TIME4 register can
decrease the number of wait states by 1 EPI clock cycle for greater
granularity. This field is used if the CSBAUD bit is enabled in the
EPIHB8CFG2 register. This field is not applicable in BURST mode.
Value Description
0x0 Active WRn is 2 EPI clocks
0x1 Active WRn is 4 EPI clocks
0x2 Active WRn is 6 EPI clocks
0x3 Active WRn is 8 EPI clocks
This field is used in conjunction with the EPIBAUD2 register.
CS3n Read Wait States
This field adds wait states to the data phase of CS3n accesses (the
address phase is not affected).
The effect is to delay the rising edge of RDn/Oen (or the falling edge of
RD). Each wait state adds 2 EPI clock cycles to the access time. The
RDWSM bit in the EPIHB8TIME4 register can decrease the number of
wait states by 1 EPI clock cycle for greater granularity. This field is used
when the CSBAUD bit is set in the EPIHB8CFG2 register.
This field is not applicable in BURST mode.
Value Description
0x0 Active RDn is 2 EPI clocks
0x1 Active RDn is 4 EPI clocks
0x2 Active RDn is 6 EPI clocks
0x3 Active RDn is 8 EPI clocks
This field is used in conjunction with the EPIBAUD2 register.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 18, 2014
959
Texas Instruments-Production Data