TM4C129XNCZAD Datasheet, PDF (1677/2191 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C129XNCZAD Microcontroller
Register 7: Ethernet MAC Flow Control (EMACFLOWCTL), offset 0x018
The Ethernet MAC Flow Control (EMACFLOWCTL) register controls the generation and reception
of the control (pause command) frames by the MAC's Flow control module. A write to a register with
the FCBBPA (bit 0) set to 1 triggers the Flow Control block to generate a pause control frame. The
fields of the control frame are selected as specified in the 802.3x specification, and the pause time
(PT) value from this register is used in the pause time field of the control frame. The FCBBPA bit is
cleared by the hardware once the control frame is transferred onto the cable. The Host must make
sure that the busy bit is clear before writing to the register.
Ethernet MAC Flow Control (EMACFLOWCTL)
Base 0x400E.C000
Offset 0x018
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
PT
Type RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
DZQP
reserved
UP
RFE
TFE FCBBPA
Type RO
RO
RO
RO
RO
RO
RO
RO
RW
RO
RO
RO
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:16
15:8
7
Name
PT
reserved
DZQP
Type
RW
RO
RW
Reset
0x0
0x0
0
Description
Pause Time
This field holds the value to be used in the pause time field in the transmit
control frame.
For example, if these bits are set to 0x0100 then 256 slot times are used
in the Pause Time field in the transmit control frame.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Disable Zero-Quanta Pause
When this bit is set, it disables the automatic generation of the
Zero-Quanta Pause Control frames on the deassertion of the flow-control
signal from the FIFO layer. When this bit is reset, normal operation with
automatic Zero-Quanta Pause Control frame generation is enabled.
Value Description
0 Automatic Zero-Quanta Pause Control generation is enabled.
1 Automatic Zero-Quanta Pause Control generation is disabled.
6:4
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 18, 2014
Texas Instruments-Production Data
1677