TM4C129XNCZAD Datasheet, PDF (1641/2191 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C129XNCZAD Microcontroller
– The Ethernet type is 0x86dd but the IP header Version field is not equal to 0x6.
– The frame ends before the IPv6 header (40 bytes) or extension header (as given in the
corresponding Header Length field in an extension header) is completely received.
If the checksum offload engine detects an IP header error, it still inserts an IPv4 header checksum
if the Ethernet Type field indicates an IPv4 payload.
24.3.9.3
Receive Checksum Offload Engine
Both IPv4 and IPv6 frames in the received Ethernet frames are detected and processed for data
integrity. The receive checksum feature can be enabled by setting the IPC bit of the Ethernet MAC
Configuration (EMACCFG) register. The EMAC receiver identifies IPv4 or IPv6 frames by checking
for value 0x0800 or 0x86DD, respectively, in the received Ethernet frames' Type field. This
identification also applies to single VLAN-tagged frames. The offline receive checksum engine
calculates IPv4 header checksums and checks that they match the received IPv4 header checksums.
The IP Header Error bit is set for any mismatch between the indicated payload type (Ethernet Type
field) and the IP header version, or when the received frame does not have enough bytes, as
indicated by the Length field of the IPv4 header or when fewer than 20 bytes are available in an
IPv4 or IPv6 header. This engine also identifies a TCP, UDP, or ICMP payload in the received IP
datagrams (IPv4 or IPv6) and calculates the checksum of such payloads properly, as defined in the
TCP, UDP, or ICMP specifications. This engine includes the TCP, UDP, or ICMPv6 pseudo-header
bytes for checksum calculation and checks whether the received checksum field matches the
calculated value. The result of this operation is given as a Payload Checksum Error bit in the receive
status word. This status bit is also set if the length of the TCP, UDP, or ICMP payload does not
match the expected payload length given in the IP header.
24.3.10
MAC Management Counters
The MAC Management Counters (MMC) module maintains a set of registers for gathering statistics
on the received and transmitted frames. The register set includes a control register for controlling
the behavior of the registers, two 32-bit registers containing interrupts generated (one for receive
and one for transmit), and two 32-bit registers containing masks for the Interrupt register (one for
receive and one for transmit).The MMC counters are free running and start counting when a
corresponding frame is received or transmitted. The MMC counter registers provided are as follows:
■ Ethernet MAC Transmit Frame Count for Good and Bad Frames (EMACTXCNTGB)
■ Ethernet MAC Transmit Frame Count for Frames Transmitted after Single Collision
(EMACTXCNTSCOL)
■ Ethernet MAC Transmit Frame Count for Frames Transmitted after Multiple Collisions
(EMACTXCNTMCOL)
■ Ethernet MAC Transmit Octet Count Good (EMACTXOCTCNTG)
■ Ethernet MAC Receive Frame Count for Good and Bad Frames (EMACRXCNTGB)
■ Ethernet MAC Receive Frame Count for CRC Error Frames (EMACRXCNTCRCERR)
■ Ethernet MAC Receive Frame Count for Alignment Error Frames (EMACRXCNTALGNERR)
■ Ethernet MAC Receive Frame Count for Good Unicast Frames (EMACRXCNTGUNI)
June 18, 2014
Texas Instruments-Production Data
1641