TM4C129XNCZAD Datasheet, PDF (1505/2191 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C129XNCZAD Microcontroller
Register 24: I²C FIFO Control (I2CFIFOCTL), offset 0xF04
The FIFO Control Register can be programmed to control various aspects of the FIFO transaction,
such as RX and TX FIFO assignment, byte count value for FIFO triggers and flushing of the FIFOs.
I2C FIFO Control (I2CFIFOCTL)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
I2C 6 base: 0x400C.2000
I2C 7 base: 0x400C.3000
I2C 8 base: 0x400B.8000
I2C 9 base: 0x400B.9000
Offset 0xF04
Type RW, reset 0x0004.0004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RXASGNMT RXFLUSH DMARXENA
reserved
RXTRIG
Type RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TXASGNMT TXFLUSH DMATXENA
reserved
TXTRIG
Type RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Bit/Field
31
Name
RXASGNMT
Type
RW
Reset
0
Description
RX Control Assignment
Value Description
0 RX FIFO is assigned to Master
1 RX FIFO is assigned to Slave
30
RXFLUSH
RW
0
RX FIFO Flush
Setting this bit will Flush the RX FIFO. This bit will self-clear when the
flush has completed.
29
DMARXENA
RW
0
DMA RX Channel Enable
Value Description
0 DMA RX channel disabled
1 DMA RX channel enabled
28:19
reserved
RO
0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 18, 2014
Texas Instruments-Production Data
1505