TM4C129XNCZAD Datasheet, PDF (635/2191 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C129XNCZAD Microcontroller
8.2
8.2.1
8.2.2
Functional Description
This section describes the functionality of the SRAM, ROM, Flash, and EEPROM memories.
Note: The μDMA has read-only access to flash (in Run Mode only).
SRAM
The internal system SRAM of the Tiva™ C Series devices is located at address 0x2000.0000 of the
device memory map. To reduce the number of time consuming read-modify-write (RMW) operations,
ARM provides bit-banding technology in the processor. With a bit-band-enabled processor, certain
regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation. The bit-band base is located at address 0x2200.0000.
The bit-band alias is calculated by using the formula:
bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4)
For example, if bit 3 at address 0x2000.1000 is to be modified, the bit-band alias is calculated as:
0x2200.0000 + (0x1000 * 32) + (3 * 4) = 0x2202.000C
With the alias address calculated, an instruction performing a read/write to address 0x2202.000C
allows direct access to only bit 3 of the byte at address 0x2000.1000.
For details about bit-banding, see “Bit-Banding” on page 120.
Note:
The SRAM is implemented using four-way 32-bit wide interleaved SRAM banks (separate
SRAM arrays) which allow for increased speed between memory accesses. When using
interleaving, a write to one bank followed by a read of another bank can occur in successive
clock cycles without incurring any delay. However, a write access that is followed immediately
by a read access to the same bank incurs a stall of a single clock cycle.
The SRAM memory layout allows for multiple masters to access different SRAM banks
simultaneously. If two masters attempt to access the same SRAM bank, the master with
the higher priority gains access to the memory bus and the master with the lower priority is
stalled by one wait state. If four masters attempt to access the same SRAM bank, access
by the master with the lowest priority is delayed by three wait states. The CPU core always
has the highest priority for SRAM memory accesses.
ROM
The internal ROM of the Tiva™ C Series device is located at address 0x0100.0000 of the device
memory map. Detailed information on the ROM contents can be found in the Tiva™ C Series
TM4C129x ROM User’s Guide (literature number SPMU363).
The ROM contains the following components:
■ TivaWare^™ Boot Loader and vector table
■ TivaWare Peripheral Driver Library (DriverLib) release for product-specific peripherals and
interfaces
■ Advanced Encryption Standard (AES) cryptography tables
■ Cyclic Redundancy Check (CRC) error detection functionality
The boot loader is used as an initial program loader (when the Flash location 0x0000.0004, the
reset vector location is all 1s (that is, erased state of Flash)) as well as an application-initiated
June 18, 2014
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