SMJ320C80_15 Datasheet, PDF (90/158 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B -- AUGUST 1998 -- REVISED JUNE 2002
block-write cycles (continued)
State
Col A
Col B
Col C
r1
r2
r3
CLKOUT
CT[2:0]
4
r6 rspin rspin col col
ci^† col
drn
r1
c1
c1
c1
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
PAC PAC Idle PAC Drain
RL
A[31:0]
Row
Col A Col B
Col C
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
D[63:0]
DBEN
DDIN
A
B
C
Sel A Sel B
Sel C
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
A
B
C
† _{Internally generated pipeline bubble (example)}
Figure 70. Pipelined 1-Cycle/Column Block-Write-Cycle Timing
90
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