SMJ320C80_15 Datasheet, PDF (134/158 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025A -- AUGUST 1998 -- REVISED JUNE 2002
local bus timing requirements: cycle configuration inputs (see Figure 111)
The cycle configuration inputs are sampled at the beginning of each row access during the r2 state. The inputs
typically are generated by a static decode of the A[31:0] and STATUS[5:0] outputs.
NO
14 t_{su(CFGV-CKOH)}
15 t_h(CKOH-CFGV)
16 t_a(MIDV-CFGV)
Setup time, AS, BS, CT, PS, and UTIME valid to CLKOUT no longer low
Hold time, AS, BS, CT, PS, and UTIME valid after CLKOUT high
Access time, AS, BS, CT, PS, and UTIME valid after memory identification
(A, STATUS) valid
MIN MAX
8
2
UNIT
ns
ns
3t_H -- 10 ns
t_H
t_H
t_H
t_H
t_H
t_H
CLKOUT
STATUS[5:0]
Cycle Type
A[31:0]
RL
AS[2:0]
Row Address
15
16
14
Valid
BS[1:0]
Valid
CT[2:0]
Valid
PS[3:0]
Valid
UTIME
Valid
Figure 111. Local Bus Timing: Cycle Configuration Inputs
134
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