SMJ320C80_15 Datasheet, PDF (141/158 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025A -- AUGUST 1998 -- REVISED JUNE 2002
local bus timing: 2-cycle/column CAS timing
These timing parameters apply to the CAS/DQM[7:0] signals during 2-cycle-per-column memory accesses
only. They should be used in place of the general output and data input timing parameters when the
2-cycle/column (nonuser-timed) cycle timing is selected (CT[2:0] inputs = 0b110). The value n as used in the
parameters represents the integral number of half cycles between the transitions of the signals in question.
NO
42 t_w(CASH)
43 t_w(CASL)
44 t_h(OUTV-CASL)
45 t_h(CASL-OUTV)
46 t_a(CASL-DV)
47 t_h(CASH-DV)
Pulse duration, CAS/DQM high
Pulse duration, CAS/DQM low
Hold time, CAS/DQM high after output valid
D[63:0]
A[31:0], STATUS[5:0]
DBEN, DDIN, DSF, RAS, RL, TRG/CAS, W
Hold time, output valid after CAS/DQM low
Access time, data valid from CAS/DQM low
Hold time, data valid after CAS/DQM high
MIN
t_H--2
3t_H--9.5
MAX
UNIT
ns
ns
nt_H--4.5
nt_H--4.0
ns
nt_H--3
nt_H--9.5
ns
3t_H--12 ns
2
ns
t_H
t_H
CLKOUT
CAS/DQM[7:0]
44
Output
D[63:0]
t_H
t_H
46
t_H
t_H
t_H
t_H
t_H
t_H
42
43
45
47
Figure 116. 2-Cycle/Column CAS Timing
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