SMJ320C80_15 Datasheet, PDF (120/158 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B -- AUGUST 1998 -- REVISED JUNE 2002
SDRAM block-write cycles (continued)
State
Col Pipe
r1
r2
r3
r5
r6 rspin
col col
col
col
col
col
r1
Col A c1
Col B
c1
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
2, 3
Cycle Type
PAC
PAC
Idle DCAB
RL
A[31:0]
Row
Col A
Col B
RAS
CAS/DQM[7:0]
A
B
DSF
TRG/CAS
A
B
W
D[63:0]
Sel A
Sel B
DBEN
DDIN
Command
ACTV
BLKW
BLKW
Figure 97. SDRAM Burst-Length 2 Block-Write Cycle Timing
DCAB
120
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