SMJ320C80_15 Datasheet, PDF (74/158 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B -- AUGUST 1998 -- REVISED JUNE 2002
DRAM-type cycles
The DRAM-type cycles are page-mode accesses consisting of a row access followed by one or more column
accesses. Column accesses may be one, two, or three clock cycles in length with two and three cycle accesses
allowing the insertion of wait states to accommodate slow devices. Idle cycles can occur after necessary column
accesses have completed or between column accesses due to “bubbles” in the TC data-flow pipeline. The
pipeline diagrams in Figure 57 show the pipeline stages for each access type and when the CAS/DQM signal
corresponding to the column access is activated.
CAS/DQM --- /A A/B B/C C/ ---
Col A c1 c2 c3
Col B
c1 c2 c3
Col C
c1 c2 c3
Idle
ci ci ci
Pipelined 1-cycle/column EDO (CT = 0000)
reads, read transfers, split read transfers
CAS/DQM A B C
Col A c1
Col B
c1
Col C
c1
Idle
ci
Pipelined 1-cycle/column (CT = 0000)
writes, load color register (LCR), block writes
CAS/DQM A B C ---
Col A c1 c2
Col B
c1 c2
Col C
c1 c2
Idle
ci ci
Nonpipelined 1-cycle/column EDO (CT = 0001)
reads, read transfers, split read transfers
CAS/DQM A B C
Col A c1
Col B
c1
Col C
c1
Idle
ci
Nonpipelined 1-cycle/column (CT = 0001)
writes, LCRs, block writes
CAS/DQM
A
B
C
Col A c1 c2 c3
--- --- ---
Col B
c1 c2 c3
--- --- ---
Col C
c1 c2 c3
--- --- ---
Idle
ci ci ci
CAS/DQM
A
B
C
Col A c1 c2
--- ---
Col B
c1 c2
--- ---
Col C
c1 c2
--- ---
Idle
ci ci
2-cycle/column EDO (CT = 0010)
reads, read transfers, split read transfers
2-cycle/column (CT = 0010)
writes, LCRs, block writes
CAS/DQM
AA
BB
CC
CAS/DQM
AA
BB
CC
Col A c1 c2 c3 c4 c5
Col A c1 c2 c3
--- --- --- --- ---
--- --- ---
--- --- --- --- ---
--- --- ---
Col B
c1 c2 c3 c4 c5
Col B
c1 c2 c3
--- --- --- --- ---
--- --- ---
--- --- --- --- ---
--- --- ---
Col C
c1 c2 c3 c4 c5
Col C
c1 c2 c3
--- --- --- --- ---
--- --- ---
--- --- --- --- ---
--- --- ---
Idle
ci ci ci ci ci
ci ci ci
3-cycle/column EDO (CT = 0011)
reads, read transfers, split read transfers
3-cycle/column (CT = 0011)
writes, LCRs, and block writes
Figure 57. DRAM Cycle Column Pipelines
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