SMJ320C80_15 Datasheet, PDF (36/158 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B -- AUGUST 1998 -- REVISED JUNE 2002
PP functional block diagram
Figure 22 shows a block diagram of a parallel processor. Key features of the PP include:
D 64-bit instruction word (supports multiple parallel operations)
D Three-stage pipeline for fast instruction cycle
D Numerous registers
-- 8 data, 10 address, 6 index registers
-- 20 other user-visible registers
D Data Unit
-- 16 x 16 integer multiplier (optional dual 8 x 8)
-- Splittable 3-input ALU
-- 32-bit barrel rotator
-- Mask generator
-- Multiple status flag expander for translations to/from 1 bit-per-pixel space.
-- Conditional assignment of data unit results
-- Conditional source selection
-- Special processing hardware
Leftmost one/rightmost one
Leftmost bit change/rightmost bit change
D Memory addressing
-- Two address units (global and local) provide up to two 32-bit accesses in parallel with data unit
operation.
-- 12 addressing modes (immediate and indexed)
-- Byte, halfword, and word addressability
-- Scaled indexed addressing
-- Conditional assignment for loads
-- Conditional source selection for stores
D Program flow
-- Three hardware loop controllers
Zero overhead looping/branching
Nested loops
Multiple loop endpoints
-- Instruction cache management
-- PC mapped to register file
-- Interrupts for messages and context switching
D Algebraic assembly language
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