TLK1201ARCP_16 Datasheet, PDF (9/24 Pages) Texas Instruments – Single Monolithic PLL Design

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TLK1201ARCP, TLK1201AIRCP
ETHERNET TRANSCEIVERS
SLLS580D – FEBRUARY 2004 – REVISED SEPTEMBER 2007
Testability
The loopback function provides for at-speed testing of the transmit/receive portions of the circuitry. The enable
function allows for all circuitry to be disabled so that an Iddq test can be performed. The PRBS function also
allows for a BIST (built-in self test). The terminal setting, TESTEN high, enables the test mode. The terminal
TESTEN has an internal pulldown resistor, so it defaults to normal operation. The TESTEN is only used for
factory testing, and is not intended for end-user control.
Loopback Testing
The transceiver can provide a self-test function by enabling (setting LOOPEN to high level) the internal loopback
path. Enabling this function causes serial transmitted data to be routed internally to the receiver. The parallel
data output can be compared to the parallel input data for functional verification. The external differential output
is held in a high-impedance state during the loopback testing.
Enable Function
When held low, ENABLE disables all quiescent power in both the analog and digital circuitry. This allows an
ultralow-power idle state when the link is not active.
PRBS Function
This device has a built-in 2⁷–1 PRBS function. When the PRBSEN control bit is set high, the PRBS test is
enabled. A PRBS is generated and fed into the 10-bit parallel transmitter input bus. Data from the normal parallel
input source is ignored during PRBS test mode. The PRBS pattern is then fed through the transmit circuitry as if
it were normal data and sent out to the transmitter. The output can be sent to a bit error rate tester (BERT) or to
the receiver of another TLK1201AI. Since the PRBS is not really random and is really a predetermined sequence
of 1s and 0s, the data can be captured and checked for errors by a BERT. This device also has a built-in BERT
function on the receiver side that is enabled by PRBSEN. It can receive a PRBS pattern and check for errors,
and then reports the errors by forcing the SYNC/PASS terminal low. When PRBS is enabled, RBCMODE is
ignored. MODESEL must be low for the PRBS verifier to function correctly. The PRBS testing supports two
modes (normal and latched), which are controlled by the SYNCEN input. When SYNCEN is low, the result of the
PRBS bit error rate test is passed to the SYNC/PASS terminal. When SYNCEN is high the result of the PRBS
verification is latched on the SYNC/PASS output (that is, a single failure forces SYNC/PASS to remain low).
JTAG
The TLK1201A supports an IEEE1149.1 JTAG function while maintaining compatibility with the industry standard
64 pin QFP package footprint. In this way, the TLK1201A installed on a board layout that was designed for the
industry standard footprint such as for the TNETE2201B. (Provided the supply voltage can be programmed from
the older 3.3 V to 2.5 V.) The JTAG pins on the TLK1201A are chosen to either be on the ‘vender-unique’ pins of
the industry standard footprint, or are on pins that were previously power or ground. The TRSTN pin has been
placed on pin 56, which is a ground on the industry standard footprint. In this way, a TLK1201A installed onto the
older footprint has the JTAG tap controller held in reset, and thus disabled. If the JTAG function is desired, then
the 5 JTAG pins TRSTN, TMS, TCK, TDI, and TDO can be used in the usual manner for a JTAG function. If the
JTAG function is not desired, then connecting TRSTN to ground is recommended. TMS and TDI have internal
pullup resistors, and can thus be left unconnected if not used. TDO is an output and should be left unconnected
if JTAG is not used. TCK does not have an internal pullup, and can be tied to GND or PWR if not used, but with
TRSTN low, this input is not used, and thus can be left unconnected.
Copyright © 2004–2007, Texas Instruments Incorporated
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Product Folder Link(s): TLK1201ARCP TLK1201AIRCP